1. Technical Field
The present invention relates to integrated circuit devices in general, and in particular to an apparatus for biasing logic circuits within integrated circuit devices. Still more particularly, the present invention relates to an apparatus for biasing ultra-low voltage logic circuits within an integrated circuit device.
2. Description of the Prior Art
Metal-oxide semiconductor field-effect transistors (MOSFETs) are commonly found in integrated circuit devices. A MOSFET includes a gate, a source, and a drain. The flow of charge carriers through a channel between the source and drain can be controlled by applying a voltage at the gate of a MOSFET. A depletion-mode MOSFET includes a doped or conducting channel under a gate even when no voltage is applied to the gate. An enhancement-mode MOSFET, in contrast, requires a gate-to-source bias voltage be applied in order to generate an inversion layer to serve as a conducting channel. Such bias voltage is known as a threshold voltage, Vt. A positive voltage between the gate and source is required to induce a strong channel for an N-channel enhancement-mode MOSFET. As for a P-channel enhancement-mode MOSFET, current flows when the gate-to-source voltage is negative below the negative threshold voltage of the P-channel enhancement-mode MOSFET.
However, even when the gate voltage is less than the threshold voltage, a current, commonly referred to as a subthreshold current, still exists within the channel and its value is given by IDS (VGS)=(W/L) I0 10xe2x88x92(Vgxe2x88x92Vt)/s, where VGS is a gate voltage with respect to a source, I0 is a constant approximately equals to 300 nA for N-channel MOSFETs and 70 nA for P-channel MOSFETs, s is the subthreshold swing xcx9c80 mV/decade, Vt is the threshold voltage, and W and L are the electrical width and length of a MOSFET, respectively.
The threshold voltage of an enhancement-mode MOSFET is determined by several intrinsic factors, such as channel length, channel width, doping, gate oxide thickness, etc. Extrinsic factors, such as ambient temperature, can also affect the threshold voltage. Furthermore, the threshold voltage is strongly influenced by the voltage applied to the substrate or well (or generally known as the body) of a MOSFET in that a more positive bias will lead to a less positive threshold voltage. If the threshold voltage of a transistor is too low, the transistor may have an unacceptable amount of leakage current when the actual supply voltage is greater than the desired supply voltage. Conversely, if the threshold voltage of a transistor is too high, then there is a reduced likelihood that the transistor will be fully turned on. Although many aspects of a semiconductor manufacturing process can be controlled, there is still a wide variation of threshold voltage values among all the many transistors within an integrated circuit device.
The switching power dissipated by complementary-metal oxide semiconductor (CMOS) circuits is given by Pactive=Cxc3x97Vdd2xc3x97f, where C is the capacitance of switching nodes, Vdd is the power supply voltage, and f is the frequency of the nodes switching. In many applications, it is desirable to reduce the switching power to either preserve power due to power supply limitations, or to reduce heating due to various cooling constraints. To this end, the switching power may be reduced by either reducing the capacitance, the frequency, or the operating voltage. Capacitance reductions are often limited by process and manufacturing constraints such as lithographic resolution and tolerances. The frequency often represents a desired output of the circuits and, as such, a reduction may prove a serious compromise to the desired end of a logic circuit. Thus, the power supply voltage remains a key variable that can allow for the reduction of active power.
Subthreshold logic, in which CMOS circuits are operated at Vdd less than Vt, has been an approach used for ultra-low power CMOS circuits where speed is not critical and Vdd can be reduced to approximately one volt. In principle, CMOS logic circuits can maintain stable operation to as low as Vdd=4xcex7kT/Qe, where h is an ideality, typically xcx9c1.4, and is affected by process details of the MOSFETs involved, k is the Boltzmann""s constant, Qe is the elementary charge of the electron, and T is the ambient temperature in Kelvin. In practice, however, CMOS logic circuits can operate at or nearby the above-mentioned limit only when the OFF currents of N-channel and P-channel MOSFETs, Ioff-N and Ioff-P, respectively, are very nearly equal to each other.
CMOS processing involves the use of independent doping steps for N-type and P-type MOSFETs as well as other process variables, which result in variation in the Vts and in turn the Ioffs of the N-type and P-type MOSFETs independent of one another. Thus, even when a process is devised to provide Ioff-N=Ioff-P nominally, there will be significant variations from one wafer to another which, in turn, limits the minimum Vdd at which such logic circuits fabricated in such a process will function. Consequently, it is desirable to provide a practical means of ensuring Ioff-N=Ioff-P by providing appropriate N-well and substrate biases in order to allow operation of CMOS logic circuits to values of Vdd approaching or equal to the theoretical limit of approximately 4xcex7kT/Qe or approximately 100 mV at room temperature. In light of such, the present disclosure describes an apparatus for providing precise threshold matching among several sub-threshold logic circuits.
It is an object of the present invention to provide an apparatus for predictably varying the Ioff ratios between N-channel and P-channel transistors for logic circuits that may accrue benefits from such condition. It is another object of the present invention to provide an apparatus for distributing the required N-well and substrate biases without using any explicit wiring or any conventional interconnect layers.
In accordance with a preferred embodiment of the present invention, an integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.